A Compiler for VLIW Architectures
Bulldog demonstrates that a symbiosis of new Very Long Instruction Word (VLIW) architectures and new compiling technology is practicable. VLIW architectures are reduced-instruction-set machines with a large number of parallel, pipelined functional units but only a single thread of control. These machines offer the promise of an immediate order-of-magnitude increase in speed for general purpose scientific computing. However, a traditional compiler can't find enough parallelism in scientific programs to utilize a VLIW effectively. The Bulldog compiler described here uses several new compilation techniques: trace scheduling to find more parallelism, memory-reference and memorybank disambiguation to increase memory bandwidth, and new code-generation algorithms. Although originally developed for VLIWs, many of the ideas in Bulldog could be applied to pipelined reduced-instruction-set architectures such as the MIPS. Ellis's experiments indicate that speed improvements of thirty to eighty percent are possible for scientific code on such machines.
Bulldog: A Compiler for VLIW Architectures is winner of the 1985 ACM Doctoral Dissertation Award.